Lookup table optimization for programming languages that target synchronous digital circuits
US11106437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Jan 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming language and a compiler are disclosed that optimize the use of look-up tables (LUTs) on a synchronous digital circuit (SDC) such as a field programmable gate array (FPGA) that has been programmed. LUTs are optimized by merging multiple computational operations into the same LUT. A compiler parses source code into an intermediate representation (IR). Each node of the IR that represents an operator (e.g. ‘&’, ‘+’) is mapped to a LUT that implements that operator. The compiler iteratively traverses the IR, merging adjacent LUTs into a LUT that performs both operations and performing input removal optimizations. Additional operators may be merged into a merged LUT until all the LUT's inputs are assigned. Pipeline stages are then generated based on merged LUTs, and an SDC is programmed based on the pipeline and the merged LUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.