3-dimensional NAND flash layer variation aware SSD raid
US11106534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.