Methods and apparatus for resisitive memory device for sense margin compensation
US11107524B2 · kind B2 · utility
0Cited by
9References
14Claims
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Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory device is provided. The resistive memory device includes a resistive memory cell electrically connected to a local word line node; a local word line transistor configured to electrically connect the local word line node to a global word line node; a global word line transistor configured to electrically connect the global word line node to a sensing node; and a margin compensation circuit comprising a margin compensation switch electrically connected to the local word line node and the global word line node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.