Group III-V semiconductor fuses and their methods of fabrication
US11107764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2017 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Nov 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.