Multi-wafer stack structure and forming method thereof
US11107794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.