Patent · US Active

Method of fabricating stacked semiconductor device

US11107812B2 · kind B2 · utility

2Cited by

9References

18Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Boon Teik Chan · Wilsele, BE
Zheng Tao · Heverlee, BE
Steven Demuynck · Aarschot, BE

Key dates

Filing date	Nov 26, 2019
Grant date	Aug 31, 2021
Priority date	—
Expiry date	Nov 29, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/01
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.