Low noise integrated circuit techniques
US11108404B1 · kind B1 · utility
7Cited by
12References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 22, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Jul 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The techniques of this disclosure can cancel or reduce the kT/C noise directly before the gain stage. The effect of the kT/C noise can be greatly reduced, allowing both lower noise conversion and smaller sampling capacitors, which can reduce the die area and reduce the power consumption of the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.