Dual dynamic random (DDR) access memory interface design for aerospace printed circuit boards
US11109485B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | May 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10545
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.