Apparatus and method and computer program product for configuring impedance of memory interfaces
US11112981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Jul 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention introduces a method for configuring impedance of memory interfaces, performed by a processing unit, including: setting a first impedance value associated with an on-die termination (ODT) for a receiver of a controller to a first default value; setting a second impedance value associated with a driver variable resistance for a transmitter of a memory device to a second default value; performing tests for test combinations each comprises a third impedance value associated with a driver variable resistance for a transmitter of the controller and a fourth impedance value associated with an ODT for a receiver of the memory device; and storing a test result for each in a predefined location of a static random access memory (SRAM), thereby enabling a calibration host to obtain the test result for each from the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.