Processing core with metadata actuated conditional graph execution
US11113051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2018 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Oct 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core comprises a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also comprises a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also comprises an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also comprises a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.