Automated concurrency and repetition with minimal syntax
US11113064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2020 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Nov 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/503
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core receives a request to execute application code including a trigger instruction and an instruction block that reads a row of data values from a data structure and outputs a data value from a function using the row as input. The data structure is divided into multiple portions and the trigger instruction indicates that multiple instances of the instruction block are to be executed concurrently. In response to the request and to identification of the instruction block and trigger instruction, the processor core generates multiple instances of a support block that causes independent repetitive execution of each instance of the instruction block until all rows of the corresponding portion of the data structure are used as input. The processor core assigns instances of the instruction and support blocks to multiple processor cores, and provides each instance of the instruction block with the corresponding portion of the data structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.