Realm identifier comparison for translation cache lookup
US11113209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2018 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Jun 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus has a translation cache (100) comprising a number of entries for specifying address translation data. Each entry (260) also specifies a translation context identifier (254) associated with the address translation data and a realm identifier (270) identifying one of a number of realms. Each realm corresponds to at least a portion of at least one software process executed by processing circuitry (8). In response to a memory access a lookup of the translation cache (100) is triggered. When the lookup misses in the cache (100), control circuitry (280) prevents allocation of address translation data to the cache when the current realm is excluded from accessing the target memory region by an owner realm specified for the target memory region. In the lookup, whether a given entry (260) matches the memory access depends on both a translation context identifier comparison and a realm identifier comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.