Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller
US11113214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.