Dispatching interrupts in a multi-processor system based on power and performance factors
US11113216B2 · kind B2 · utility
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Key dates
| Filing date | Mar 5, 2020 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Mar 5, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.