FPGA hardware-based secure computing method and apparatus
US11113423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2021 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Jan 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An FPGA hardware device obtains encrypted data of each participant of a secure computing system, where the FPGA hardware device stores at least one first key, where the at least one first key is at least one first key of all participants in the secure computing system or at least one first key of a predetermined number of trusted managers in the secure computing system, where the FPGA hardware device includes an FPGA chip. The FPGA hardware device decrypts the encrypted data of each participant by using a working key of each participant, to obtain plaintext data of each participant, where the working key of each participant is obtained based on a corresponding first key of the at least one first key. The FPGA hardware device performs computing based on the plaintext data of each participant to obtain a computing result. The FPGA hardware device outputs the computing result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.