Hybrid high-voltage low-voltage FinFET device
US11114348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2018 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.