Array substrate and manufacturing method thereof
US11114477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/311
Abstract
In a method for manufacturing an array substrate, a first photoresist pattern is formed on a buffer layer of a non-display region and the buffer layer uncovered by the first photoresist pattern is removed to form a first via hole in the non-display region. A second via hole is formed on the basis of the first via hole. The second via hole is connected to the first via hole. By forming the first via hole in the non-display region and forming the second via hole on the basis of the first via hole, completeness of film layers is ensured and product yield is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.