Patent · US Active

Enhancement-mode high electron mobility transistor

US11114537B2 · kind B2 · utility

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2References

20Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Steve Stoffels · Haasrode, BE
Niels Posthuma · Elewijt, BE
Brice De Jaeger · Leuven, BE

Key dates

Filing date	Jan 21, 2020
Grant date	Sep 7, 2021
Priority date	—
Expiry date	Jan 21, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/411
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.