Memory structure and manufacturing method thereof
US11114570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2020 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Apr 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02645
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.