Photonic chip passed through by a via
US11114818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Jun 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/10
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A photonic chip includes an optical layer bonded, at a bonding interface, to an interconnection layer, the thickness of the optical layer being smaller than 15 μm, a primary via that extends through the interconnection layer solely between a lower face and the bonding interface, an electrical terminal chosen from the group consisting of an electrical contact embedded in the interior of the optical layer and of an electrical track produced on an upper face, a second via that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer from the bonding interface to the electrical terminal, the maximum diameter of this secondary via being smaller than 3 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.