System and method for integrated circuit usage tracking circuit with fast tracking time for hardware security and re-configurability
US11115022B2 · kind B2 · utility
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9References
17Claims
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Key dates
| Filing date | May 6, 2016 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Dec 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An accelerated aging circuit is described to shorten the required stress time to a few seconds of operation. Due to the challenges posed by process variation in advanced CMOS technology, a stochastic processing methodology is also described to reduce the failure rate of the tracking and detection. Combining both circuit and system level acceleration, the creation of a silicon marker can be realized within seconds of usage in contrast with days of operation from previously reported aging monitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.