Interconnect circuit methods and devices
US11116070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2018 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Jul 24, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49156
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.