Substrate bias generating circuit
US11119522B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2020 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Aug 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A substrate bias generating circuit is provided for generating a substrate bias to a body of a transistor of a functional circuit. The substrate bias generating circuit includes a first transistor and a second transistor which are connected in series between a supply voltage terminal and a ground terminal, and control terminals of the first transistor and the second transistor are coupled to each other. A third transistor includes a terminal electrically coupled to body of one of the first transistor and the second transistor, and another terminal coupled to the body. A resistance element is connected between the terminal of the third transistor and a current input terminal of the first transistor or a current output terminal of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.