Execution unit configured to evaluate functions using at least one multiplier circuit
US11119733B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Jan 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution unit for a processor, the execution unit comprising: a look up table; a preparatory circuit configured to determine an index value in dependence upon the operand and search the look up table using the index value to locate an entry comprising a natural logarithm associated with the index value; control circuitry configured to provide a first value determined in dependence upon the operand and a second value determined in dependence upon the operand as inputs to at least one multiplier circuit of the execution unit so as to evaluate terms of a Taylor series expansion of a natural logarithm, wherein the control circuitry is configured to provide the natural logarithm associated with the index value and the terms of the Taylor series expansion as inputs to at least one addition circuit so as to generate a mantissa of a natural logarithm of the operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.