Methods for depositing III-V compositions on silicon
US11120990B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 20, 2020 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Jul 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02647
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method that includes directing a first precursor that includes a Group III element and a second precursor that includes a Group V element to a chamber containing crystalline silicon, where the crystalline silicon includes a substantially planar surface that is patterned with a plurality of v-grooves and the directing results in the forming of a III-V crystal preferentially on a (111) Si surface of the crystalline silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.