Voltage doubler using a switching regulator and voltage limiter
US11121625B2 · kind B2 · utility
1Cited by
4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/0093
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A voltage doubler circuit configuration includes a switching regulator having a variable input voltage and a regulated voltage, and a voltage doubler circuit that utilizes the regulated voltage of the switching regulator. The voltage doubler circuit includes an output capacitor that receives an elevated voltage from a voltage doubler capacitor and an electrical clamp that limits the voltage doubler capacitor from exceeding the regulated voltage. The output voltage is twice the regulated voltage minus circuit losses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.