Method for paralleled SiC power switching devices based on wiring optimization
US11126773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2020 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Sep 18, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a design method for paralleled SiC power switching devices based on wiring optimization which belongs to the field of power electronics technology, aiming at the problem that in the existing scheme of paralleled SiC devices, the optimal performance of SiC devices cannot be presented with paralleled multiple SiC devices due to limitations of the unequal switching losses and transient currents. The design method comprises at least three wiring separation slots being arranged in parallel and in sequence on a PCB circuit board; wherein a power half-bridge composed of two SiC devices is arranged in each wiring separation slot, thereby increasing a parasitic inductance between adjacent power half-bridges. The disclosure can improve the current sharing performance of the switching transient current existing in the application of multiple paralleled SiC devices, so that SiC devices can be applied to high-power and high-current power electronic converters stably and reliably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.