Deep trench isolation and substrate connection on SOI
US11127622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2020 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Jan 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.