Electronic package with stud bump electrical connections
US11127706B2 · kind B2 · utility
1Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.