Semiconductor devices
US11127730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2019 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.