Method to improve HKMG contact resistance
US11127833B2 · kind B2 · utility
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3References
20Claims
0Family size
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Key dates
| Filing date | Nov 25, 2019 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Nov 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes providing a substrate, forming a gate structure including a metal gate on the substrate, forming an interlayer dielectric layer on the gate structure, forming a first contact hole extending through the interlayer dielectric layer to expose a surface of the metal gate, and removing a portion of the metal gate using a wet etching process to form a second contact hole having a cross-sectional size larger than a cross-sectional size of the first contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.