Constant Vds1 bias control for stacked transistor configuration
US11128261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Feb 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.