High linearity and low voltage input buffer circuit
US11128291B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/567
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor MN1 and MN3 as well as MN2 and MN6, auxiliary buffer comprised of PMOS transistors MP1 and MP3 as well as MP2 and MP4, replica current amplifier comprised of NMOS transistors MN3 and MN4 as well as MN5 and MN6. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.