Clock and data recovery device and jitter tolerance enhancement method thereof
US11128304B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2020 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | May 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.