Background duty cycle error measurement for RF DAC
US11128310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2020 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | May 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches and/or errors. The mismatches and/or errors can degrade the quality of the analog output. To extract the mismatches and/or errors, a transparent dither can be used. The mismatches and/or errors can be extracted by observing the analog output, and performing a cross-correlation of the observed output with a switching bit stream of the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the respective mismatches and/or errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.