White box AES implementation
US11128436B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2017 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Jul 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor device with a white-box masked implementation of the cryptographic algorithm AES implemented thereon, which comprises a SubBytes transformation. The white-box masked implementation is hardened in that white-box round input values x′ are supplied at the round input of rounds instead of the round input values x, said white-box round input values being formed from a concatenation of: (i) the round input values x that are masked by means of the invertible masking mapping A and (ii) obfuscation values y that are likewise masked with the invertible masking mapping A; wherein from the white-box round input values x′ only the (i) round input values x are fed to the SubBytes transformation T, and (ii) the masked obfuscation values y are not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.