Integrated photonic test circuit
US11131710B2 · kind B2 · utility
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1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Jan 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/425
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A photonic circuit testing device, including a photonic test chip including, on the side of a first surface of the chip: micropillars, each intended to be placed in contact with a corresponding electric connection pad of the photonic circuit; and first optical input/output ports, each intended to be optically coupled to a second corresponding optical input/output port of the photonic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.