Patent · US Active

Timer control for peripheral component interconnect express components implemented with thunderbolt controllers

US11132319B2 · kind B2 · utility

0Cited by
1References
25Claims
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Assignee

Inventors

Key dates

Filing dateJan 12, 2018
Grant dateSep 28, 2021
Priority date
Expiry dateJan 29, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04B10/27
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.