Method and device for neural architecture search optimized for binary neural network
US11132600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2020 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Nov 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a target network by performing neural architecture search using optimized search space is provided. The method includes steps of: a computing device (a) if a target data is inputted into the target network, allowing the target network to apply neural network operation to the target data, to generate an estimated search vector; and (b) allowing a loss layer to calculate architecture parameter losses by referring to the estimated search vector and a ground truth search vector, and to perform backpropagation by referring to the architecture parameter losses to update architecture parameter vectors for determining final layer operations among candidate layer operations included in an optimized layer type set corresponding to the optimized search space and wherein the final layer operations are to be performed by neural blocks, within cells of the target network, arranged according to an optimized cell template corresponding to the optimized search space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.