Non-volatile memory semiconductor device with electrostatic discharge protection, planarization layers, and manufacturing method thereof
US11133188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Dec 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.