Semiconductor devices including a thick metal layer
US11133253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2020 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | May 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.