Gate-lifted NMOS ESD protection device
US11133299B2 · kind B2 · utility
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3References
19Claims
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Assignee
Inventors
Key dates
| Filing date | Oct 4, 2018 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Apr 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/184
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.