Multi-bit magnetic memory device
US11133458B2 · kind B2 · utility
1Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Jan 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory device. A memory device according to an embodiment of the present invention includes a memory device including a substrate; and a lower electrode, seed layer, lower synthetic antiferromagnetic layer, magnetic tunnel junction, upper synthetic antiferromagnetic layer, and upper electrode that are laminated on the substrate, wherein the magnetic tunnel junction includes a lower pinned layer, lower tunnel barrier layer, lower free layer, separation layer, upper free layer, upper tunnel barrier layer and upper pinned layer that are sequentially laminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.