Asynchronous SAR ADC using two-stage comparator having separate resets
US11133812B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Oct 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.