Quasi-cyclic LDPC coding and decoding method and apparatus, and LDPC coder and decoder
US11133826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2017 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Nov 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.