PAM-based coding schemes for parallel communication
US11133874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2020 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Jan 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Encoders and decoders for encoding and decoding data according to a coding scheme. The encoder converts N bits of input data into M voltage signals for transmission over M parallel wires to a decoder having one or two decoding stages that recover the N bits of data from the M voltage signals. The coding scheme is an N-bit, M-wire PAM-Q code in which each voltage signal wi has one of Q voltage levels l1-lQ, where l1<l2< . . . <lQ, and the different sets of M voltage signals for the different N-bit input values are permutations of a single set of M voltage signals. The decoder has a comparator stage. For the decoder having one other decoding stage, the other decoding stage is a computation stage or a logic stage that is before or after the comparator stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.