Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline
US11138008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jan 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions. One embodiment of a processor comprises: a decoder to decode a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode and first and second source operands, and having a split value associated therewith; and execution circuitry to execute the operations of the decoded broadcast instruction to copy a first data element specified by the first source operand to each of a first set of contiguous data element locations in a destination register and to copy a second data element specified by the second source operand to a second set of contiguous data element locations in the destination register, wherein the first and second sets of contiguous data element locations are determined in accordance with the split value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.