Loop management in multi-processor dataflow architecture

US11138010B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Chia-Yu Chen · White Plains, US
• Jungwook Choi · Seoul, KR
• Brian W. Curran · Saugerties, US
• Bruce M. Fleischer · Mount Kisco, US
• Kailash Gopalakrishnan · San Jose, US
• Jinwook Oh · Fort Lee, US
• Sunil K. Shukla · Scarsdale, US
• Vijayalakshmi Srinivasan · New York, US

Key dates

• Filing date: Oct 1, 2020
• Grant date: Oct 5, 2021
• Expiry date: Oct 1, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/325
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present invention include a computer system that manages execution of one or more programs with one or more loops where each loop having a loop level. Embodiments that manage loops that can skip execution and the number of loops changing during execution are also disclosed. A loop level register (LLEV) stores the loop level for a currently executing loop. A Loop-Back Program Counter Register (LBPR) has a table of one or more Loop-Back Registers. Each Loop-Back Register stores the loop level for a LBPR respective loop and a loop back PC location for the LBPR respective loop. A Program Counter points back to the PC location for each iteration of the loop. A Loop Current Count Register table (LCCR) tracks a number of iterations remaining to executed for of the loop. A loop management process causes one of the CPUs to execute all the one or more instructions of an iteration of the currently executing program loop. When all iterations of the executing loop are complete, the LLEV is decremented to a next loop level that contained the executed loop.