Clock fractional divider module, image and/or video processing module, and apparatus
US11138054B2 · kind B2 · utility
0Cited by
3References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Mar 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock fractional divider module which is formed as, comprises or has integrated therein a dual-core lock step unit. The dual-core lock step unit is configured in order to realize a clock fractional division arrangement, mechanism or process accompanied by an error detection, recognition and/or correction arrangement, mechanism or process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.