Parity swapping to DRAM
US11138066B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | May 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The A storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. A first command to write data to a first stream is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first stream. When a second command to write data to a second stream is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second stream is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second stream. The updated second XOR data is copied from the RAM1 to the RAM2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.